As a method of encoding or decoding moving picture data by employing a band compression technique, there are MPEG systems (Moving Picture Coding Experts Group) discussed and standardized by ISO-IEC/JTCI/SC2/wGll. In these MPEG systems, it is fundamental to utilize the intra-picture correlation, to divide a picture into blocks each comprising plural pixels, perform a discrete cosine conversion as an orthogonal conversion systems and a processing of quantization and Huffman coding to data of each block, thereby realizing the compression of image data. The pixels which are obtained by performing those processings can not be reproduced the original pixels prudently even if the inverse processing is performed, as a result, the pixels existing at the boundary parts of adjacent two blocks have different values. Thereby, block noises are generated.
In MPEG4, a deblocking filter has been standardized as a countermeasure against this problem. This filter is constituted to have two kinds of operation modes, in a case where the one dimensional window having the block boundary at its center is provided as shown in FIG. 4. In FIG. 4, g(n) (n is an integer from 0 to 9) denotes pixel data of ten pixels next to one other with the block boundary at the center. This filter performs the adaptive switching of those operation modes according to the activity of the block boundary neighboring pixels. The following evaluation function is employed for the switching of the operation mode.    f=φ{g(0)−g(1)+φ{g(1) g(2)}    +φ{g(2)−g(3)}+φ{g(3)−g(4)}    |φ{g(4)−g(5)}+φ{g(5)−g(6)}    +φ{g(6)−g(7)}+φ{g(7)−g(8)}    φ{(g(8)−g(9)};    here, i f(|×|<=Th1(=2)}            φ(x)=1;        else        φ(x)=0;Th denotes a threshold value. The operation mode is switched as follows employing the evaluation function.            if (f>−Th2 (=6))            DC offset mode;        else        default mode;The DC offset mode shown here is an operation mode in case where the changing of the pixel data existing at the block boundary is calm, and the default mode is an operation mode in case where the changing of the pixel data existing at the block border is drastic. With respect to the DC offset mode, the filter shown in the following is defined.            coef(1)=1:    coef(2)=1:    coef(3)=2:    coef(4)=2:    coef(5)=4:    coef(6)=2:    coef(7)=2:    coef(8)=1:    coef(9)=1:Then, the following filtering processing is performed to obtain the processed pixel g′ (m) (m=1, 2, 3, 4, 5, 6, 7, 8) MA X=max (g(1), g(2), g(3), g(4), g(5), g(6), g(7), g(8)):MIN=min (g(1), g(2), g(3), g(4), g(5), g(6), g(7), g(8)):if(|MAX−MIN|<2*QP)
i f ( | M A X − M I N | < 2 * Q P ){min_padding = | g ( 0 ) − g ( 1 ) | < Q P ? g ( 0 ) : g ( 1 ) ;max_padding = | g ( 8 ) − g ( 9 ) | < Q P ? g ( 9 ) : g ( 8 ) ;g′ ( m ) = 0 ;f o r ( i =− 4 ; i < 5 ; i ++ )g′ ( m ) += coef( i + 4 ) *( m + i < 1 ? min_padding :( m + i > 8 ? max_padding : g ( m + i ) ) ) ;g′ ( m ) = n i n t ( g′ ( m ) / 1 6 ) ;}e l s eg′ ( m ) = g ( m ) ;else                g′ (m)=g(m);Here, QP denotes a quantization parameter of a macro block to which a pixel value of g(5) belongs. Further, min_padding and max_padding are, as defined in the above-described equations, values which are obtained respectively from the first pixel data g(1) and the eighth pixel data g(8), and the pixel data g(0) and the pixel data g(9), which are adjacent at outside the pixel data g(1) and the pixel data g(8), respectively. This filtering is performed to all horizontal edges, and thereafter, performed to all vertical edges. In this filtering processing, when            for(i=−4; i<5; i++)            g′(m)+−coef (i+4)*                    (m+1<1? min_padding:            (m+i>8? max_padding: g(m)1)))                            g′(m)=n int (g′(m)/16): are carried out by software in a general purpose arithmetic device included in the processor, the flow as shown in FIG. 3 is obtained.
Hereinafter, the flow shown in FIG. 3 will be described. At first, by a start instruction, the value m out of eight pixels g(m), to which the arithmetic processing is to be carried out, is set (step S1). Next, the value i is set (step S2). As the initial value for i, i=−4 is set. Subsequently, whether i is 5 or not is detected (step S3), and when i is not 5, m and i are added (step S4). Then, when m+i is smaller than 1 in step S5, min_padding data is written into the memory and 1 is added to i (step S6). Further, when m+i is larger than or equal to 1, m+i and 8 are compared in step S7, and when m+i is larger than 8, max_padding data is written into the memory and 1 is added to i (step S8). When m+i is smaller than or equal to 8, g(m+i) data is written into memory and 1 is added to i (step S9). For each value of m, these operations are repeated nine times in total, i.e., while the value i changes from −4 to 4, and when the value of i is 5, multiplication and addition are performed to nine data which have been written into the memory until then (step S10), and the result is shifted by 4 bits in step S11, thereby a result obtained by performing the filtering processing, i.e., the pixel data obtained by performing the filtering processing are output.
However, in the filtering processing performed by the conventional general purpose arithmetic device, a result is output by repeating by nine times in total for i from −4 to 4, for each value of m. In order to output this one result, 67 cycles are required at the maximum. In addition, there are 8 values from 1 to 8 for the value of m, and therefore, 536 cycles that is obtained by multiplying 67 cycles by 8 are required, thereby resulting in an increase in the arithmetic cycle number, which further results in the processing.
The present invention is made to solve the above-described problems, and has for its object to provide a deblocking filter arithmetic apparatus having a less arithmetic cycle number.